Figure 3 shows the equivalent circuit of the reverse conduction and reverse conduction characteristic. Figure 3a shows the current path and current density distribution at reverse conduction state. The reverse current in the FDMOS flows through the fin-shaped diode, while the current conduct by the body diode in Con. MOS. According to Fig. 3b, the fin-shaped diode as an FWD exhibits a much lower VON of 0.66 V (@1 A/cm2) in the FDMOS than 2.99 V of the Con. MOS. However, the current capacity (above point O) of the Con. MOS is higher than that of the FDMOS since the Con. MOS works in a bipolar conduction mode, which introduces greater reverse recovery loss nevertheless. The body diode doesn’t conduct because the voltage drop on the body diode for the FDMOS is lower than its turn-on voltage at the reverse conduction state.

Fig. 3
figure 3

a Equivalent circuit and current density distribution (@VDS =  − 4 V) of the reverse conduction. b Reverse conduction characteristics (log-scale and linear-scale) of the FDMOS and the Con. MOS

Figure 4 shows the analysis of breakdown characteristics. BV is defined as the VDS @ 10−6A/cm2. As shown in Fig. 4a, the FDMOS achieves a hard avalanche breakdown voltage of 1791 V. The fin-shaped diode has a very low reverse leakage current of ~ 10−7 A/cm2 at VDS =  − 1600 V, and the switching current ratio (Ion/Ioff) is over 1010. The leakage current and the barrier height (ΦB) satisfy the I  exp(− ΦB/kt) relation. Figure 4b shows the extracted conduction band energy along the middle of fin channel at different VDS values. The width of barrier decreases with the increasing VDS, and the barrier height decreases almost linearly. The holes generated by the avalanche breakdown enter the fin channel region leads to the increase in the fin potential, and thus, the barrier height decreases rapidly. Therefore, the leakage current increases rapidly and the breakdown occurs.

Fig. 4
figure 4

a Breakdown mechanism analysis of the fin-shaped diode. Linear curve fitting of the current density (ID) and barrier height (ΦB). The a and b are the coefficients. b Simulated conduction band energy extracted from the cutline at different VD values

Figure 5 shows the impacts of Lfin and Wfin on ΦB and reverse conduction characteristics for the FDMOS. As shown in Fig. 5a, ΦB decreases with the increase in Wfin and increases with the increase in Lfin because of the increasing overlap of the depletion region. A high ΦB is beneficial to achieving a high breakdown voltage, but it leads to the high VON. In addition, the fin channel mobility is low, and thus, the resistance increases with the increase in Lfin, as shown in Fig. 5b. Considering the trade-off between breakdown characteristics and on-state performance, the optimized Lfin and Wfin is 0.8 μm and 0.2 μm, respectively.

Fig. 5
figure 5

Influence of the Lfin and Wfin on a ΦB and b JSD for the FDMOS

Figure 6 shows the gate charge characteristics of the two devices. The QGD of the FDMOS is 114 nC/cm2, which is far less than 264 nC/cm2 of the Con. MOS. One reason is that the overlap area between the gate and drain is reduced. The other is that the source metal surrounding the fin can effectively shield the gate-drain overlap, and thus, part of the capacitance between gate and drain (CGD) transforms to the capacitance between gate and source (CGS) for the FDMOS.

Fig. 6
figure 6

Simulated gate charges. The inset figure shows the test circuit

Figure 7a shows that the FDMOS achieves better reverse recovery characteristics and lower reverse recovery loss. Figure 7b compares the hole distribution of the FDMOS and the Con. MOS during reverse recovery. The FDMOS device is in unipolar mode, and thus, the hole concentration in the drift region is very low, which is far less than n-drift concentration (1 × 1016 cm−3). However, the drift region of the Con. MOS has a high hole concentration due to the minority injection. Compared with the Con. MOS, the FDMOS reduces the Qrr from 1.64 to 1.36 μC, and reduces trr from 170 to 86 ns as shown in Fig. 7a.

Fig. 7
figure 7

Comparison of a reverse recovery characteristic and b hole distribution during reverse recovery

Figure 8a shows the test circuit for switching characteristic. The Switch 1 (S1) and the Switch 2 (S2) are the same device, and they can be the proposed FDMOS or the Con. MOS. The gate and the source of the S1 is short-circuited as the FWD diode, and a parasitic inductor Lp = 10 nH is connected with S1 to simulate the overvoltage caused by reverse recovery of the FWD diode. Figure 8b, c shows power dissipation and turn-on/off curves. The tr of the FDMOS and the Con. MOS are 52 ns and 126 ns, respectively. The current rise rate of the FDMOS and the Con. MOS is almost the same, and the voltage drop rate of the FDMOS is much higher than that of the Con. MOS due to the smaller QGD. Therefore, the Eon of the FDMOS reduces by 33.8% in comparison with the Con. MOS. Owing to the low QGD, as shown in Fig. 6, the Eoff of the FDMOS reduces from 11.08 to 5.11 mJ, decreasing by 53.8% in comparison with that of the Con. MOS.

Fig. 8
figure 8

a Test circuit for turn-on/off process. P-i-N diode acts as FWD in the Con. MOS. Fin diode acts as FWD in the FDMOS. Simulation of the b turn-on and c turn-off transient for the FDMOS and the Con. MOS

The key process steps have been given out to show that the structure is doable, as shown in Fig. 9. The required GaN epi layer was proposed and fabricated in REF [19]. Firstly, the n-GaN drift region is grown by metalorganic chemical vapor deposition (MOCVD), and the P-GaN region is formed by implantation of Mg ion, as shown in Fig. 9a, b. Then, the top GaN layer is regrown by plasma-MBE. The p-GaN regions are used as the P-base region. Secondly, the fin is formed by Cl2/BCl3-based inductively coupled plasma (ICP) etching, and Al2O3 dielectric is formed by ALD, as shown in Fig. 9d. The oxide etch depth is controlled by a timed photoresist (PR) etch [20]. The mask is photoresist, treated with O2 plasma as shown in Fig. 9e, f. Then the Al2O3 dielectric is etched down by buffered oxide etch (BOE) to expose top n+ surface and the mask is removed, as shown in Fig. 9g, h. Complete FDMOS structure with implanted n+ source/drain, metal electrodes and anode metal is not drawn in Fig. 9.

Fig. 9
figure 9

Key fabrication process flows for the FDMOS. ac GaN epi layer growth [19]; d ICP etch to form the fin and deposit the Al2O3 dielectric; eh Expose top n+ surface

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